The physical layout of a deep submicron VLSI design has to adhere to certain design rules (or design constraints) dictated mostly by the technology used to fabricate the design. It is the task of a design rule checker (DRC) tool/module to ensure that a given layout confirms to an applicable set of design rules. The rules, provided by the manufacturer and specific to a process node, are required to ensure manufacturability and yield. If the layout does not adhere to one or more of these rules, then the DRC tool informs the designer about the design rule violations. The designer must fix each of the design rule violations before the design is considered design rule clean.
The use of double patterning technology (DPT) or dual masking adds to the complexity of the manufacturing. The manufacturing problem in dual masking systems requires DRC tools to be able to detect “odd loops” formed by shapes violating certain rules in the design. However, current designs are utilizing triple masking and conventional DRC tools cannot detect triple pattern technology (TPT) spacing violations which are different from DPT odd loop violations.
Therefore, there is a strong need for a solution that overcomes the aforementioned issues. The present invention addresses such a need.